1. Field of the Invention
The present invention relates to a method of controlling an integrated semiconductor memory device and circuit arrangement for carrying out same and, more particularly, to a method of controlling memory cells designed and arranged in accordance with merged transistor logic (MTL) techniques.
2. Description of the Prior Art
In German Pat. No. 25 11 518, methods and circuit arrangements are described for controlling an integrated semiconductor memory, the memory cells of which consist of flipflops with bipolar transistors and of Schottky diodes as read/write coupling elements and which, as load elements, use highly ohmic resistors or transistors connected as current sources. The write/read cycles of such arrangements are executed in several phases and are selected by level changes on word lines and bit lines which, for increasing the writing speed and the reading speed as well as for reducing the power dissipation, execute the discharge of the bit lines via the conductive memory cell transistors. The bit lines are discharged to ground via the conductive memory cell transistors, and during the reading phase of the memory the bit lines are re-stored only slightly so that the re-stored current flowing through the memory cell is very low.
In the field of logic circuits and memory techniques using bipolar transistors there has been substantial developments in recent years producing great interest in the industry, particularly those developments defined in the literature as MTL (merged transistor logic) or I.sup.2 L (integrated injection logic). For typical examples of such logic circuit and memory designs reference is made to the IEEE Journal of Solid-State Circuits, Vol. SC/7, No. 5, October 1972, pp. 340ff and 346ff and U.S. Pat. Nos. 3,736,477 and 3,816,758. These designs, using bipolar transistors, are characterized by short switching times and are suitable for the layout of extremely highly integrated memories and logic arrays.
For an example of a further memory cell, reference is made to German Offenlegungsschrift No. 2,307,739. This memory cell is composed of two logic circuits wherein the collector of the inverting transistor of the one circuit is respectively coupled to the base of the inverting transistor of the other circuit. The two transistors are operated inversely and form the actual flipflop transistors. As a load element for both flipflop transistors the complementary transistor, connected via a separated line of each basic circuit, is used via the injection of the minority charge carriers, i.e. the current supply is effected. For addressing, i.e. for writing-in and reading-out of the memory cell, the base of each flipflop transistor is additionally connected to the emitter of the associated additional, equally complementary addressing transistor whose collector is applied to the associated bit line and whose base is applied to the address line.
German Offenlegungsschrift No. 2,612,666 discloses, with the use of an additional transistor, a highly integrated, inverting logic circuit with a zone sequence forming an inverting transistor. The inverting transistor is controlled (via an injection zone adjacent to the base-emitter junction) through the injection of load carriers with supply voltage, and at the base, said circuit is characterized in that connected to the injection zone a sense circuit is provided by way of which the conductive state of the inverting transistor is sensed on the basis of the current pre-injected into the injection area with the transistor being conductive.
Memories comprising cells showing an MTL-type structure require, in the selection of a cell, the re-charging of bit data and/or control line capacitances. The voltage swing of the bit lines corresponds approximately to the voltage swing of the selected word line. As already described in German Pat. No. 25 11 518, the capacitive discharge currents are discharged to ground via the memory cells of the selected word line and via the word line driver. However, with a high number of memory cells within a matrix this has the disadvantage that the surface area required for the driver circuit, the electric power dissipation for each driver, and delay time in the selection of the word line are, impractically, too high.